Abstract: When low-voltage and high-voltage domain coexist on a single chip, the electro static discharge protection architecture must be comprehensively designed. It is particularly important to cover all possible discharge paths to ensure circuit protection. Based on the actual design scheme of a chip under silicon on insulator (SOI) process, this article elaborates on the design architecture of electrostatic protection for the situation of multiple voltage domains coexisting, and introduces in detail the discharge paths of the protection circuits of each module and the configuration of transmission line pulse (TLP) generator parameters.The actual sample passes the electrostatic test standard required by the demand. This has significant reference value for new product development under similar development requirements backgrounds.

Key words: low-voltage domain; high-voltage domain; electro static discharge protection; GGNMOS; GDPMOS; snapback circuit

摘要： 在高压域和低压域功能模块共存的产品中，静电放电防护架构需要得到更加全面的考 虑，做好各种可能路径的静电泄放尤为重要。该文章基于绝缘体上硅（SOI）工艺下的一款芯 片的实际设计方案，对多电压域共存情况的静电防护做出了设计架构的阐述，详细介绍各模 块防护电路泄放路径及传输线脉冲（TLP）发生器参数配置，实际样品通过了需求的静电测 试标准。这对类似开发需求背景下的新产品研发具有重要的参考意义。

关键词: 低压域；高压域；静电放电防护；GGNMOS；GDPMOS；滞回特性电路